module key (
    input   wire        clk             ,
    input   wire        rst_n           ,
    input   wire        up_key          ,
    input   wire        left_key        ,
    input   wire        right_key       ,
    input   wire        down_key        ,
    output  reg         rotate          ,
    output  reg         left            ,
    output  reg         right           ,
    output  reg         down 
);

reg [3:0] shift_up;
reg [3:0] shift_left;
reg [3:0] shift_right;
reg [3:0] shift_down;
reg clk_div;
reg [7:0] clk_cnt;

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        shift_up <= 4'b0;
    else
        shift_up <= {shift_up[2:0],up_key};
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        shift_left <= 4'b0;
    else
        shift_left <= {shift_left[2:0],left_key};
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        shift_right <= 4'b0;
    else
        shift_right <= {shift_right[2:0],right_key};
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        shift_down <= 4'b0;
    else
        shift_down <= {shift_down[2:0],down_key};
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin
        clk_div <= 1'b0;
        clk_cnt <= 8'b0;
    end
    else if(clk_cnt == 8'd50)begin
        clk_cnt <= 8'd0;
        clk_div <= ~clk_div;
    end
    else begin
        clk_cnt <= clk_cnt + 1'b1;
        clk_div <= clk_div;
    end
end

always @(posedge clk_div or negedge rst_n) begin
    if(!rst_n)begin
        rotate <= 0;
        left <= 0;
        right <= 0;
        down <= 0;
    end
    else begin
        rotate <= shift_up[3];
        left <= shift_left[3];
        right <= shift_right[3];
        down <= shift_down[3];
    end
end
endmodule